星期一	星期二	星期三	星期四	星期五	星期六	星期日
第1節
第2節
第3節
第4節
第5節
第6節
第7節
第8節
第9節
第10節
第11節
第12節
第13節

1.國立陽明交通大學電子物理學系博士後研究員 2008/10～2016/02
2.國立交通大學前瞻光電研究中心助理研究員 2016/03～2017/12
3.國立陽明交通大學光電系助理研究員 2018/01～2020/01
4.逢甲大學電子工程系專任助理教授 2020/02～2023/01
5.國立勤益科技大學電子工程系專任助理教授 2023/02~迄今

半導體奈米元件、非揮發性記憶體、半導體製程與技術

1. 半導體元件物理 
2. 低溫複晶矽元件與技術
3. 金屬氧化物半導體元件與技術
4. 先進半導體奈米電子元件與積體電路製程技術
5. 記憶體電子元件與技術

電子學
電路學
半導體元件物理
半導體薄膜工程與元件
記憶體元件

International Regular Journal:
[1] Zhen-Hao Li, Tsung-Che Chiang, Po-Yi Kuo, Chun-Hao Tu, Yue Kuo and Po-Tsun Liu*, “Heterogeneous Integration of Atomically-Thin Indium Tungsten Oxide Transistors for Low-Power 3D Monolithic Complementary Inverter,” Advanced Science,Volume 10, Issue 9, 2205481,March 2023.Impact Factor: 17.521
[2] Po-Yi Kuo*, Zhen-Hao Li, Chien-Min Chang, and Po-Tsun Liu, “Extraction method for equivalent oxide thickness of a thin high-κ gate insulator and estimation of field-effect mobility in amorphous oxide semiconductor nano-sheet junctionless transistors,” IEEE Trans. Electron Devices, vol. 69, no. 9, pp.4791–4795, Sept. 2022.(Corresponding author)  Impact Factor: 3.221
[3] Wan-Ta Fan, Po-Tsun Liu, Po-Yi Kuo, Chien-Min Chang, I-Han Liu, and Yue Kuo, “Numerical Analysis of Oxygen-Related Defects in Amorphous In-W-O Nanosheet Thin-Film Transistor,”Nanomaterials, vol.11, 3070, Nov. 2021. doi: 10.3390/nano11113070. Impact Factor: 5.719
[4]Po-Yi Kuo*, Shao-Chi Lo, Hsiu-Hsuan Wei, and Po-Tsun Liu, “Asymmetric low metal contamination Ni-induced lateral crystallization plycrystalline-silicon thin-film transistors with low OFF-state currents for back-end of line (BEOL) compatible devices applications,”IEEE Journal of the Electron Devices Society, vol.8, pp.1317–1322, Oct. 2020.(Corresponding author) Impact Factor: 2.523
[5] Chuan-Hui Shen, Wei-Yen Chen, Shen-Yang Lee, Po-Yi Kuo, and Tien-Sheng Chao, “Nitride induced stress affecting crystallinity of sidewall damascene gate-all-around nanowire poly-Si FETs,”IEEETrans. Nanotechnology, vol. 19,pp.322–327, March2020. Impact Factor: 2.967
[6] Shen-Yang Lee, Han-Wei Chen, Chiuan-Huei Shen, Po-Yi Kuo, Chun-Chih Chung, Yu-En Huang, Hsin-Yu Chen, and Tien-Sheng Chao, “Effect of seed layer on gate-all-around poly-Si nanowire negative-capacitance FETs with MFMIS and MFIS structures: planar Capacitors to 3-D FETs,”IEEE Trans. Electron Devices, vol. 67, no. 2, pp.711–716, Feb. 2020. Impact Factor: 3.221
[7] Po-Yi Kuo, Chien-Min Chang, I-Han Liu, and Po-Tsun Liu, “Two-dimensional-like amorphous indium tungsten oxide nano-sheet junctionless transistors with low operation voltage,” Scientific Reports, vol. 9, No. 7579, May 2019. Impact Factor: 4.996
[8] Dun-Bao Ruan, Po-Tsun Liu, Yu-Chuan Chiu, Min-Chin Yu, Kai-Jhih Gan, Ta-Chun Chien, Yi-Heng Chen, Po-Yi Kuo, Simon M.Sze, “Performance improvements of tungsten and zinc doped indium oxide thin film transistor by fluorine based double plasma treatment with a high-k gate dielectric,” Thin Solid Films, vol. 665, pp. 117–122, Nov. 2018. Impact Factor: 2.358
[9] Dun-Bao Ruan, Po-Tsun Liu, Kai-Jhih Gan, Yu-Chuan Chiu, Min-Chin Yu, Ta-Chun Chien, Yi-Heng Chen, Po-Yi Kuo, Simon M.Sze, “The influence on electrical characteristics of amorphous indium tungsten oxide thin film transistors with multi-stacked active layer structure,” Thin Solid Films, vol. 666, pp. 94–99, Nov. 2018.Impact Factor: 2.358
[10] Dun-Bao, Ruan, Po-Tsun Liu, Yu-Chuan Chiu, Kai-Zhi Kan, Min-Chin, Yu, Ta-Chun Chien, Yi-Heng Chen, Po-Yi Kuo, Simon M. Sze, “Investigation of low operation voltage InZnSnO thin-film transistors with different high-k gate dielectric by physical vapor deposition,” Thin Solid Films, vol. 660, pp. 885–890, Aug. 2018. Impact Factor: 2.358
[11] Dun-Bao, Ruan, Po-Tsun Liu, Yu-ChuanChiu, Po-Yi Kuo, Min-Chin, Yu, Kai-Zhi Kan, Ta-Chun Chien, Chen, Yi-Heng Chen, Simon M. Sze, “Effect of interfacial layer on device performance of metal oxide thin-film transistor with a multilayer high-k gate stack,” Thin Solid Films, vol. 660, pp. 578–584, Aug. 2018. Impact Factor: 2.358
[12] Po-Tsun Liu, Chih-Hsiang Chang, Po-Yi Kuo, and Po-Wen Chen, “Effects of Backchannel passivation on electrical behavior of hetero-stacked a-IWO/IGZO thin film transistors,” ECS Journal of Solid State Science and Technology, vol. 7, Q17-Q20, March 2018. Impact Factor: 2.483
[13] Dun-Bao Ruan, Po-Tsun Liu, Yu-Chuan Chiu, Po-Yi Kuo, Min-Chin Yu, Kai-jhih Gan, Ta-Chun Chien and Simon M. Sze, “ Mobility enhancement for high stability tungsten doped indium-zinc oxide thin film transistors with a channel passivation layer,”RSC Advances, vol. 8, no. 13, pp. 6925–6930, Feb. 2018. Impact Factor: 4.036
[14] Dong-Ru Hsieh, Yi-De Chan, Po-Yi Kuo, and Tien-Sheng Chao, “ Investigation of channel doping concentration and reverse boron penetration on P-type pi-gate poly-Si junctionless accumulation mode FETs,”IEEE Journal of the Electron Devices Society, vol.6, pp.314–319, Feb. 2018. Impact Factor: 2.352
[15]Don-Ru Hsieh, Jer-Yi Lin, Po-Yi Kuo, and Tien-Sheng Chao, “Comprehensive analysis on electrical characteristics of Pi-gate poly-Si junctionless FETs,” IEEE Trans. Electron Devices, vol. 64, no. 7, pp.2992–2998, July 2017. Impact Factor: 3.221
[16] Don-Ru Hsieh, Po-Yi Kuo, Jer-Yi Lin, Yi-Hsuan Chen, Tien-Shun Chang, and Tien-Sheng Chao, “High-performance strained channel-sidewall damascened tri-gate poly-Si FETs with strain proximity free technique and stress memorization technique,” Semiconductor Science and Technology, vol.32, no.2, 25004, January, 2017. Impact Factor: 2.048
[17] Jer-Yi Lin, Po-Yi Kuo*, Ko-Li Lin, Chun-Chieh Chin, and Tien-Sheng Chao, “Junctionless poly-Si nanowire transistors with low-temperature trimming process for monolithic 3-D IC application,” IEEE Trans. Electron Devices, vol. 63, no. 12, pp.4998–5003, Dec. 2016. (Corresponding Author) Impact Factor: 3.221
[18] Dong-Ru Hsieh, Jer-Yi Lin, Po-Yi Kuo, and Tien-Sheng Chao, “High- Performance Pi-Gate Poly-Si Junctionless and Inversion Mode FET,” IEEE Trans. Electron Devices, vol. 63, no. 11, pp.4179–4184, Nov. 2016. Impact Factor: 3.221
[19]Po-Yi Kuo*,Yi-Hsien Lu, Tien-Sheng Chao, “High-performance GAA sidewall- damascened sub-10-nm in-situ n⁺ doped poly-Si NWs channels junctionless FETs,” IEEE Trans. Electron Devices, vol. 61, no. 11, pp.3821–3826, Nov. 2014.(Corresponding author) Impact Factor: 3.221
[20]Yi-Hong Wu, Je-Wei Lin, Yi-Hsien Lu, Rou-Han Kuo, Li-Chen Yen, Yi-Hsuan Chen, Chia-Chun Liao, Po-Yi Kuo and Tien-Sheng Chao,“ Reliability analysis of symmetric vertical channel nickel-salicided poly-Si thin-film transistors,” IEEE Trans. Electron Devices, vol. 59, no. 8, pp.2160–2166, Aug. 2012. Impact Factor: 3.221
[21]Yi-Hong Wu, Po-Yi Kuo*,Yi-Hsien Lu, Yi-Hsuan Chen, Tsung-Yu Chiang,Kuan-Ti Wang, Li-Chen Yen, and Tien-Sheng Chao,“ Symmetric vertical channel nickel-salicided poly-Si thin-film transistors with self-aligned oxide over-etching structures,” IEEE Trans. Electron Devices, vol. 58, no. 7, pp.2008–2013, July 2011.(Corresponding author) Impact Factor: 3.221
[22] Tsung-Yu Chiang, Yi-Hong Wu, William Cheng-Yu Ma, Po-Yi Kuo, Kuan-Ti Wang, Chia-Chun Liao, Chi-Ruei Yeh, Wen-Luh Yang and Tien-Sheng Chao,“Characteristics of SONOS-type flash memory with in-situ embedded silicon nanocrystals,” IEEE Trans. Electron Devices, vol. 57, no. 5, pp.1895–1902, Aug. 2010. Impact Factor: 3.221
[23]Po-Yi Kuo*, Yan-Syue Huang, Yi-Hsien Lue, Tien-Sheng Chao, and Tan-Fu Lei,“ The characteristics of n- and p-channel poly-Si thin-film transistors with fully Ni-salicided S/D and gate structure,” Journal of The Electrochemical Society, 157, H113-H119, Jan. 2010.(Corresponding author) Impact Factor: 4.386
[24] Mei-Chun Liu, Tsung-Yu Chiang, Po-Yi Kuo, Ming-Hong Chou, Yi-Hong Wu, Hsin-Chiang You, Ching-Hwa Cheng, Sheng-Hsien Liu, Wen-Luh Yang, Tan-Fu Lei and Tien-Sheng Chao,“ SONOS memories with embedded silicon nanocrystals in nitride,” Semicond. Sci. Technol., Volume : 23 Issue : 7, no. 075033, July 2008. Impact Factor: 2.048
[25] Po-Yi Kuo, Tien-Sheng Chao, Pei-Shan Hsieh, and Tan-Fu Lei,“ Characteristics of self-aligned Si/Ge T-gate poly-Si thin-film transistors with high ON/OFF current ratio,” IEEE Trans. Electron Devices, vol. 54, no. 5, pp.1171–1176, May 2007. Impact Factor: 3.221
 
International Letter Journal:
[1] Po-Yi Kuo*, “One-transistor poly-Si memory devices with near-zero subthreshold swing and extended retention time,” IEEE Electron Device Lett., vol. 45, no. 6, pp.1008–1011, Nov. 2024. Q1, Impact Factor: 4.816
[1] Shen-Yang Lee, Han-Wei Chen, Chiuan-Huei Shen, Po-Yi Kuo, Chun-Chih Chung, Yu-En Huang, Hsin-Yu Chen, and Tien-Sheng Chao, “Experimental demonstration of stacked gate-all-around poly-Si nanowires negative capacitance FETs with internal gate featuring seed layer and free of post-metal annealing process,” IEEE Electron Device Lett., vol. 40, no. 11, pp.1708–1711, Nov. 2019. Q1, Impact Factor: 4.816
[2] Chiuan-Huei Shen, Po-Yi Kuo, Chun-Chih Chung, Sen-Yang Lee, and Tien-Sheng Chao, “Stacked sidewall-damascene double-layer poly-Si trigate FETs with RTA-improved crystallinity,”IEEE Electron Device Lett., vol. 39, no. 4, pp.512–515, April 2018. Q1, Impact Factor: 4.816
[3] Yi-Hsuan Chen, Li-Chen Yen, Tien-Shun Chang, Tsung-Yu Chiang, Po-Yi Kuo, and Tien-Sheng Chao, “Low temperature polycrystalline - silicon tunneling thin-film transistors with MILC,” IEEE Electron Device Lett., vol. 34, no. 8, pp.1017–1019, Aug.2013. Q1, Impact Factor: 4.816
[4] Yi-Hsien Lu, Po-Yi Kuo*, Je-Wei Lin, Yi-Hong Wu, Yi-Hsuan Chen, and Tien-Sheng Chao, “High-performance poly-Si thin-film transistors with L-Fin channels,”IEEE Electron Device Lett., vol. 33, no. 2, pp.215–217, Feb.2012. (Corresponding author) Q1, Impact Factor: 4.816
[5]Yi-Hsien Lu, Po-Yi Kuo*, Yi-Hong Wu, Yi-Hsuan Chen, and Tien-Sheng Chao,“ Novel sub-10-nm gate-all-around Si nanowire channel poly-Si TFTs with raised source/drain,”IEEE Electron Device Lett., vol. 32, no. 2, pp.173–175, Feb.2011. (Corresponding author) Q1, Impact Factor: 4.816
[6]Yi-Hsien Lu, Chao-Hsin Chien, Po-Yi Kuo, Ming-Jui Yang, Hsiao-Yi Lin, and Tien-Sheng Chao,“High-performance poly-Si TFTs of top-gate with high-kappa metal-gate combine the laser annealed channel and glass substrate,” Electrochem. Solid-State Lett., Volume 14, Issue 1, pp. H17-H20, 2011. Impact Factor: 2.321
[7] Yi-Hong Wu, Po-Yi Kuo*, Yi-Hsien Lue, Yi-Hsuan Chen, and Tien-Sheng Chao,“ Novelsymmetric vertical channel Ni-salicided poly-Si thin-film transistors with high ON / OFF current ratio,”IEEE Electron Device Lett., vol. 31, no. 11, pp.1233–1235, Nov. 2010. (Corresponding author) Q1, Impact Factor: 4.816
[8]Kuan-Ti Wang, Tien-Sheng Chao, Tsung-Yu Chiang, Woei-Cherng Wu, Po-Yi Kuo, Yi-Hong Wu, Yu-Lun Lu, Chia-Chun Liao, Wen-Luh Yang, Chien-Hsing Lee, Tsung-Min Hsieh, Jhyy-Cheng Liou, Shen-De Wang, Tzu-Ping Chen, Chien-Hung Chen, Chih-Hung Lin, and Hwi-Huang Chen,“ Physical mechanism of high- programming-efficiency dynamic-threshold source-side injection in wrapped- select-gate SONOS for NOR-type flash memory,”IEEE Electron Device Lett., vol. 30, no. 11, pp.1206–1208, Nov. 2009. Q1, Impact Factor: 4.816
[9]Tsung-Yu Chiang, Ming-Wen Ma, Yi-Hong Wu, Po-Yi Kuo, Kuan-Ti Wang, Chia-Chun Liao, Chi-Ruei Yeh, and Tien-Sheng Chao,“ MILC-TFT with high-κ dielectrics for one-time-programmable memory application,”IEEE Electron Device Lett., vol. 30, no. 9, pp.954–956, Sept. 2009. Q1, Impact Factor: 4.816
[10]Po-Yi Kuo*, Tien-Sheng Chao, Jiou-Teng Lai, Tan-Fu Lei,“Vertical n-Channel poly-Si thin-film transistors with symmetric S/D fabricated by Ni-silicide-induced lateral-crystallization technology,”IEEE Electron Device Lett., vol. 30, no. 3, pp.237–239, March 2009.(Corresponding author) Q1, Impact Factor: 4.816
[11]Po-Yi Kuo*, Tien-Sheng Chao, Jyun-Siang Huang, Tan-Fu Lei,“ Poly-Si thin-film transistor nonvolatile memory using Ge nanocrystals as a charge trapping layer deposited by the low-pressure chemical vapor deposition,”IEEE Electron Device Lett., vol. 30, no. 3, pp.234–236, March 2009.(Corresponding author) Q1, Impact Factor: 4.816
[12] Hsin-Chiang You, Po-Yi Kuo, Fu-Hsiang Ko, Tien-Sheng Chao, and Tan-Fu Lei,“ The impact of deep Ni salicidation and NH3 plasma treatment on nano-SOI FinFETs,” IEEE Electron Device Lett., vol. 27, no. 10, pp.799–801, Oct. 2006. Q1, Impact Factor: 4.816
[13] Po-Yi Kuo, Tien-Sheng Chao, Ren-Jie Wang, and Tan-Fu Lei,“ High performance poly-Si TFTs with fully Ni-self-aligned silicided S/D and gate structure,” IEEE Electron Device Lett., vol. 27, no. 4, pp. 258–261, Apr. 2006. Q1, Impact Factor: 4.816
[14] Po-Yi Kuo, Tien-Sheng Chao, and Tan-Fu Lei,“ Suppression of the floating-body effect in poly-Si thin-film transistors with self-aligned Schottky barrier source and ohmic body contact structure,” IEEE Electron Device Lett., vol. 25, no. 9, pp.634–636, Sept. 2004. Q1, Impact Factor: 4.816
[15] Hsiao-Wen Zan, Ting-Chang Chang, Po-Sheng Shih, Du-Zen Peng, Po-Yi Kuo, Tiao-Yuan Huang, Chun-Yen Chang, and Po-Tsun Liu,“ Short-channel poly-Si thin-film transistors with ultrathin channel and self-aligned tungsten-clad source/drain,” Electrochem. Solid-State Lett., Volume 7, Issue 2, pp. G31-G33, 2004. Impact Factor: 2.321
[16] Hsiao-Wen Zan, Ting-Chang Chang, Po-Sheng Shih, Du-Zen Peng, Po-Yi Kuo, Tiao-Yuan Huang, Chun-Yen Chang, and Po-Tsun Liu,“ A study of parasitic resistance effects in thin-channel polycrystalline silicon TFTs with tungsten-clad source/drain,” IEEE Electron Device Lett., vol. 24, no. 8, pp.509–511, Aug. 2003. Q1, Impact Factor: 4.816

International Conference:
[1] Po-Yi Kuo*, and Hao-Yu Wang, “Complementary poly-Si thin-film transistors fabricated using Ni-induced crystallization technology through an ultra-thin oxide Layer,” 2024 International Conference on Solid State Devices and Materials (2024SSDM), Himeji, Japan, Sept. 2024, pp. 845–846. (Post/First Author and Corresponding author)
[2] Po-Yi Kuo*, Ching-Long Huang, Guan-Lin Guo, Hao-Yu Wang, Yu-Cheng Chou, Yu-Ming Chiu, Zhen-Jie Hong, “Low Ni accumulation symmetric S/D vertical n-Channel poly-Si thin-film transistors fabricated using dual offset Ni seeding windows and discrete Ni formation technology,” 2023 International Conference on Solid State Devices and Materials (SSDM2023), Nagoya, Japan, Sept. 2023, pp. 247–248. (Oral presentation / Corresponding author)
[3] Po-Yi Kuo*, Po-Yang Huang, Yu-Cheng Chou, Cing-Long Huang, Yu-Ming Chiu, “Implantation-free vertically stacked GAA poly-Si nanosheet FETs with raised source/drain,” 2022 International Conference on Solid State Devices and Materials (SSDM2022), Chiba, Japan, Sept. 2022, pp. 303–304. (Oral presentation / Corresponding author)
[4] Po-Yang Huang, Yu-Cheng Chou, Cing-Long Huang, Yu-Ming Chiu, and Po-Yi Kuo, “Novel Nickel-Induced Crystallization Poly-Si TFTs Using a Ultra-Thin Oxide Filter,” 2021 International Electron Devices & Materials Symposium (IEDMS2021), Nov., 2021.(Corresponding author)
[5] Shen-Yang Lee, Han-Wei Chen, Chun-Chih Chung, Chiuan-Huei Shen, Po-Yi Kuo, Yu-En Huang, Hsin-Yu Chen, Tien-Sheng Chao, “Investigation of the Impact of Internal Metal Gate –From MFM Capacitors to Two-Layer-Stacked GAA Poly-Si NW FE-FETs, “ 2020 VLSI-TSA Symposium, Hsinchu, Aug. 2020, pp. 124–125.
[6] Po-Yi Kuo, Ji-Lin Wang, Zhen-Hao Li, Po-Tsun Liu, “Symmetric Ni-induced lateral crystallization poly-Si TFTs with low metal contaminations, “2018 International Conference on Solid State Devices and Materials (SSDM2018), Tokyo, Sept. 2018, pp. 791–792.
[7] Dun-Bao Ruan, Po-Tsun Liu, Yu-Chuan Chiu, Min-Chin Yu, Kai-jhih Gan, Ta-Chun Chien, Po-Yi Kuo, and Simon M. Sze, “High Mobility Tungsten-Doped Thin-Film Transistor on Polyimide Substrate with Low Temperature Process,” 2018 7th IEEE International Symposium on Next-generation electronics (ISNE),May. 2018, pp. 367–368.
[8] Po-Yi Kuo*, Chien-Min Chang, and Po-Tsun Liu, “Low thermal budget amorphous indium tungsten oxide nano-sheet junctionless transistors with near ideal subthreshold swing,”inVLSI Symp. Tech. Dig. (VLSI), June, 2018, pp. 21–22 (Corresponding author)
[9] Chiuan-Huei Shen, Po-Yi Kuo, Sen-Yang Lee and Tien-Sheng Chao, “Stacked sidewall-damascene poly-Si trigate FETs with RTA improved crystallinity,” International Electron Devices & Materials Symposium (IEDMS),Sept., 2017.
[10]Po-Yi Kuo*, Jer-Yi Lin, and Tien-Sheng Chao, “Implantation Free GAA Double Spacer Poly-Si Nanowires Channel Junctionless FETs with Sub-1V Gate Operation and Near Ideal Subthreshold Swing,”in Proc. IEEE Int. Electron Devices Meeting (IEDM), Dec. 2015, pp. 133–136 (Corresponding author)
[11] Po-Yi Kuo, Jer-Yi Lin, Juo-Li Yang, Yi-Hsien Lu, and Tien-Sheng Chao, “Comparison of gate-all-around sidewall damascened nanowires and fin-like poly-Si channels with sharp corner structure on SONOS memory devices,”International Symposium on Next-Generation Electronics (ISNE), pp. 64., H1–2, 2014.
[12]Yi-Hsuan Chen, Je-Wei Lin, Li-Chen Yen, Rou-Han Kuo, Yi-Hsien Lu, Yi-Hong Wu, Po-Yi Kuo, and Tien-Sheng Chao, “Double-gated junctionless vertical channel poly-Si thin-film transistors,”2012 International Conference onSolid State Devices and Materials (SSDM2012), Kyoto, Japan, PS–1–12.
[13] Yi-Hsien Lu, Po-Yi Kuo*, Yi-Hong Wu, Yi-Hsuan Chen, Tien-Sheng Chao,“ Novel GAA raised source / drain sub-10-nm poly-Si NW channel TFTs with self-aligned corked gate structure for 3-D IC applications,” inVLSI Symp. Tech. Dig. (VLSI), June 2011, Kyoto, Japan, pp. 142–143.(Corresponding author)
[14]Yi-Hsien Lue, Chao-Hsin Chien, Po-Yi Kuo, Ming-Jui Yang, Hsiao-Yi Lin, and Tien-Sheng Chao,“ High-performance (S.S.<100 mV/dec) poly-Si TFTs with laser annealed channel and high-κ metal-gate on glass substrate,”2010 Solid State Devices and Materials (SSDM2010), Tokyo, Japan, pp. P–3–25.
[15]Yi-Hsien Lue, Po-Yi Kuo,Yi-Hong Wu, and Tien-Sheng Chao, “High- performance poly-Si TFTs with novel FinFet-like channel,”2010 International Conference onSolid State Devices and Materials (SSDM2010), Tokyo, Japan, pp.P–1–18.
[16] Po-Yi Kuo, Tien-Sheng Chao, Jyun-Siang Huang, and Tan-Fu Lei,“ A new poly-Si thin-film transistor nonvolatile Ge nanocrystal memory with high programming/erasing efficiency,” 2007 International Thin Film Transistors Conference in conjunction with SID-Mid Europe Chapter Spring Meeting (ITC07), pp.188–191.
[17] Po-Yi Kuo, Tien-Sheng Chao, Yan-Syue Huang, and Tan-Fu Lei,“ Characteristics of poly-Si thin-film transistors with fully Ni-self-aligned silicided source/drain and gate structure,” 2006 International Electron Devices and Materials Symposium (IEDMS2006), symposium C, pp. 207–208.
[18] Po-Yi Kuo, Tien-Sheng Chao, and Tan-Fu Lei,“ Characteristics of poly-Si thin-film transistors with self-aligned Schottky barrier source and ohmic body contact structure,” 2004 International Electron Devices and Materials Symposium (IEDMS2004), pp. 301–304. (Best student paper award)

114年度
複晶矽鰭式近零次臨界擺幅記憶體元件關鍵技術開發
(NSTC 114-2221-E-167-047)

113年度
(NSTC 113-2221-E-167-025)

109~111年度
可應用於三維積體電路之後段製程相容元件技術開發
(MOST 109-2222-E-035-006-MY3)

1.美國專利US 8,445,348 B1: A MANUFACTURING METHOD OF A SEMICONDUCTOR COMPONENT WITH A NANOWIRE CHANNEL
發明人: 郭柏儀，趙天生，呂宜憲
2.日本專利特許第5532071號:ナノワイヤチャネルを有する半導体装置の製造方法およびこの装置を用いた半導体装置の製造方法
發明人: 郭柏儀，趙天生，呂宜憲
3.中華民國專利證書號 I467666: 申請號: 100149225: 具有奈米線通道之半導體元件的製程及藉此形成之半導體元件
發明人: 郭柏儀，趙天生，呂宜憲
4.中華民國專利證書號 I805116, 申請號: 110145689: 垂直堆疊型互補式薄膜電晶體
發明人: 劉柏村，李振豪，蔣宗哲，郭柏儀